1. Field of the Invention
A semiconductor integrated circuit device according to the present invention relates particularly to a semiconductor integrated circuit device including SRAM (Static Random Access Memory) cells arranged in an array.
2. Description of Related Art
These years, products (for example, a single-unit SRAM product and a MPU) each manufactured by mounting SRAM cells on a semiconductor integrated circuit device have been widely in use. For the purpose of increasing the number of SRAM cells mounted thereon, attempts are made to form the gate electrodes of the respective transistors and the diffused layers constituting each SRAM cell in as simple a shape as possible, and thus to miniaturize the elements. Examples of such an SRAM cell are disclosed by Patent Documents 1 to 6. Each of the SRAM cells respectively disclosed by Patent Documents 1 to 6 has a cell shape long in the word-line direction. By contrast, there are SRAM cells each having a cell shape long in the bit-line direction. For this reason, in the following descriptions, SRAM cells each having a cell shape long in the word-line direction will be referred to as “horizontally-long cells” whereas SRAM cells each having a cell shape long in the bit-line direction will be referred to as “vertically-long cells.” Patent Documents 1 to 6 disclose their respective horizontally-long cells each in which an n-well region is interposed between the p-well regions.
Patent Document 3 discloses that the well regions are supplied with their well potentials through a silicide layer. Patent Document 4 discloses that the well regions are supplied with their well potentials through their butted contacts, respectively. According to Patent Document 4, such a potential supply scheme prevents a latch-up. Patent Documents 5 and 6 disclose that the source regions of the driver transistors formed in the different p-well regions are connected together, respectively. This connecting scheme makes the source potentials of the transistors formed in the remote locations equal to each other, respectively. This makes it possible to stabilize the operations of the driver transistors.
[Patent Document 1] Japanese Patent Application Publication No. Hei. 10-178110
[Patent Document 2] Japanese Patent Application Publication No. 2001-28401
[Patent Document 3] Japanese Patent Application Publication No. 2003-23112
[Patent Document 4] Japanese Patent Application Publication No. 2005-347360
[Patent Document 5] Japanese Patent Application Publication No. 2006-339480
[Patent Document 6] Japanese Patent Application Publication No. 2007-19166